Synthesis and FPGA-based Implementation of Hierarchical Finite State Machines from Specification in Handel-C
نویسنده
چکیده
The paper suggests a technique, which permits to describe modular, hierarchical and parallel algorithms in Handel-C. This opportunity has been provided by generating the required control sequences with the aid of a hierarchical finite state machine. The proposed specification in Handel-C is synthesizable and it can be translated (for example, in DK2 environment of Celoxica) to EDIF format. The latter can be converted to a bit-stream for commercially available FPGAs. An example of sorting procedure was described in detail and implemented in Xilinx Spartan II XC2S200 FPGA available on Celoxica RC100 prototyping board. Key-Words – hierarchical finite state machines, system-level specification, Handel-C, FPGA
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